Semiconductor memory devices are commonly found in many industrial and consumer electronics products. An increasing demand for higher memory capacity coupled with a requirement for smaller sizes results in a desire for memory with a density that is difficult to attain. As a result, multiple memory devices are often connected together to satisfy large memory requirements. Such multi-device memory systems can be implemented together in a single package (i.e., a multi chip system) or a multiplicity of memory device packages grouped together on a printed circuit board.
When multiple semiconductor memory devices are interconnected to function as a single system, a controller manages data flow between the individual memory devices and external interfaces providing requests for storing data, accessing data and manipulating data in the system. A command structure is used by the controller to provide those requests to the individual memory devices containing the data. The command structure may be dependent on the configuration of the interconnected memory devices and can impact performance of the system. For example, if the individual memory devices are in communication with the controller via a common bus, then only one of the individual memory devices may be asserted at any given time. If the individual memory devices are serially interconnected in a chain configuration with only one memory device connected to the controller, then commands for memory devices located later in the chain may be significantly delayed by earlier memory devices performing commands that cannot be interrupted. In a configuration of series-connected memory devices, the processing of a command at one device halts all transmission of commands onto subsequent memory devices, resulting in a suspension of any additional processing in the system.